This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
addr/data: 8 8
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-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File :
-- Autor :
-- Date :
--
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-- Description :
--
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
entity VHDL_Component is
port(
------------------------------------------------------------------------------
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
------------------------------------------------------------------------------
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_vector(3 downto 0) -- output vector example
);
end VHDL_Component;
--------------------------------------------------------------------------------
--Complete your VHDL description below
architecture type_architecture of VHDL_Component is
begin
end type_architecture;
library ieee;
use ieee.std_logic_1164.all;
entity TCL_Generic is
port(
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end TCL_Generic;
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4a e008 2a0 f400 e008 2a0 f400 e008
2a0 f400 903f 903f 19e 903f 19f 903f
41 144 9202 198 903f 145